Introduction

On May 6, 2025, TSMC unveiled its next-generation 2.5D chipset integration platform, dubbed CoWoS-X. This platform is designed to support ultra-high-bandwidth AI accelerators using up to eight logic dies and six HBM4 stacks. The announcement came during the TSMC Technology Symposium in Santa Clara and signals the foundry’s boldest step yet in redefining compute packaging.

“We’re not just stacking silicon—we’re composing AI systems on interposers,” said Kevin Zhang, SVP of Business Development at TSMC.¹ With CoWoS-X, TSMC promises 4X the memory bandwidth and 2X the die-to-die connectivity versus previous CoWoS generations. The platform targets workloads involving trillion-parameter models and exascale graph reasoning.

TSMC confirmed that NVIDIA, AMD, and Tenstorrent are the first customers for CoWoS-X, and production is expected in early 2026. Samsung and Intel Foundry Services are expected to respond with rival 2.5D offerings later this year.

Why it matters now

• AI accelerator demand is shifting from monolithic chips to chiplet-based architectures.
• Energy and yield constraints favor 2.5D integration over traditional SoCs.
• Memory proximity is now a key determinant of AI throughput.

Call-out: Packaging becomes the performance frontier

According to internal tests shared at the symposium, TSMC’s CoWoS-X enables 3.6 TB/s bandwidth across chipsets and reduces interconnect power by 45%.

Business implications

System architects must now design with packaging in mind—not just processor selection. CoWoS-X opens new frontiers for modular AI hardware, where logic, memory, and IO dies can be optimized and swapped independently.

This also enables faster upgrade cycles for hyperscalers and HPC buyers: rather than waiting for full-node redesigns, AI boards can mix chipsets from multiple vendors within a common CoWoS-X framework.

Looking ahead

TSMC also works with EDA vendors like Synopsys and Cadence to create AI-driven chiplet layout tools for CoWoS-X packaging. Analysts expect CoWoS-X will become a de facto standard in advanced AI and HPC design within two years.

Gartner predicts that by 2029, over 75% of high-end AI compute modules will use advanced packaging—up from 20% in 2024.

The upshot: TSMC’s CoWoS-X redefines the floor plan of disruption. Chiplets aren’t just a workaround—they’re the new substrate of scalable, efficient AI. Organizations that adopt this modular mindset now will shape the future of infrastructure agility.

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¹ Kevin Zhang, TSMC Technology Symposium keynote, May 6, 2025.