Introduction

On May 25, 2025, Synopsys and Ansys announced a groundbreaking integration of AI into electronic design automation (EDA), enabling real-time co-optimization of chip architectures and advanced packaging. This marks the industry’s first AI-powered “chip-package co-design” stack, reducing design cycles for 2.5D and 3D semiconductors from months to weeks.

“Chiplet-era design needs concurrent thinking,” said Synopsys CEO Sassine Ghazi.¹ “You can’t tape out a great die without knowing the thermal and mechanical life of the package.”

Using generative AI, the system proposes thermal-aware interposer layouts, signal integrity tuning, and AI-driven routing constraints, drastically accelerating the co-design loop. It’s compatible with Synopsys’ Fusion Compiler and Ansys’ RedHawk and Icepak solvers.

Why it matters now

• 2.5D and 3D packaging are reshaping high-performance computing and AI accelerators.
• EDA has historically been siloed, with electrical and physical domains handled separately.
• AI enables a closed-loop optimization where package feedback shapes chip floorplans in real time.

Call-out: EDA is becoming an AI problem—not just an engineering one

In internal benchmarks, Synopsys reports a 48% reduction in power noise violations and a 61% improvement in first-pass package design convergence.

Business implications

Chipmakers and fabless firms can now build more performant, power-efficient packages without adding physical iterations. Time-to-market drops, and backend bottlenecks shrink.

Foundries and system integrators get consistent simulation data across the silicon/package boundary—improving reliability forecasts and reducing thermal escapes in production.

Looking ahead

The integrated platform enters beta in July with AMD, MediaTek, and Northrop Grumman support. Full availability is planned for early 2026, with a roadmap to support photonics and chiplet verification by late next year.

Gartner projects that by 2030, over 70% of HPC and AI silicon will be designed using AI-augmented EDA tools, up from just 11% in 2023.

The upshot: With this launch, Synopsys and Ansys signal that the next leap in chip performance won’t just come from silicon, but from smarter tools that design the whole system. Disruption isn’t at the fab—it’s at the design desk.

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¹ Sassine Ghazi, Synopsys-Ansys Joint Release, May 25, 2025.